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| Freescale Semiconductor Product Preview Document Number: MC33926 Rev. 7.0, 6/2007 5.0 A Throttle Control H-Bridge The 33926 is a monolithic H-Bridge Power IC designed primarily for automotive electronic throttle control, but is applicable to any lowvoltage DC servo motor control application within the current and voltage limits stated in this specification. The 33926 is able to control inductive loads with currents up to 5.0 A peak. RMS current capability is subject to the degree of heatsinking provided to the device package. Internal peak-current limiting (regulation) is activated at load currents above 6.5 A 1.5 A. Output loads can be pulse width modulated (PWM'ed) at frequencies up to 20 kHz. A load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller's A/D input. A Status Flag output reports undervoltage, overcurrent, and overtemperature fault conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two independent disable inputs are provided to force the H-Bridge outputs to tri-state (high impedance off-state). An invert input changes the IN1 and IN2 inputs to LOW = true logic. Features 33926 AUTOMOTIVE THROTTLE H-BRIDGE ACTUATOR/ MOTOR EXCITER Bottom View SCALE 2:1 PNB SUFFIX (Pb-FREE) 98ARL10579D 32-PIN PQFN * 8.0 V to 28 V Continuous Operation (Transient Operation from 5.0 V to 40 V) * 225 m maximum RDS(ON) @ 150C (each H-Bridge MOSFET) ORDERING INFORMATION * 3.0 V and 5.0 V TTL / CMOS Logic Compatible Inputs Temperature Device Package * Overcurrent Limiting (Regulation) via Internal Constant-Off-Time Range (TA) PWM PC33926PNB/R2 - 40C to 125C 32 PQFN * Output Short Circuit Protection (Short to VPWR or Ground) * Temperature-Dependant Current-Limit Threshold Reduction * All Inputs have an Internal Source/Sink to Define the Default (Floating Input) States * Sleep Mode with Current Draw < 50 A (with Inputs Floating or Set to Match Default Logic States) * Pb-Free Packaging Designated by Suffix Code PNB VDD VPWR 33926 SF FB IN1 IN2 VPWR CCP OUT1 MOTOR OUT2 PGND AGND MCU INV SLEW D1 D2 EN Figure 1. 33926 Simplified Application Diagram *This document contains certain information on a product under development. Freescale reserves the right to change or discontinue this product without notice (c) Freescale Semiconductor, Inc., 2007. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWR LOGIC SUPPLY VDD CCP VCP CHARGE PUMP TO GATES HS1 HS2 OUT1 OUT2 EN IN1 IN2 D2 D1 INV SLEW SF FB AGND GATE DRIVE AND PROTECTION LOGIC HS1 LS1 HS2 LS2 VSENSE ILIM PWM LS1 LS2 PGND CURRENT MIRROR AND CONSTANT OFF-TIME PWM CURRENT REGULATOR PGND Figure 2. 33926 Simplified Internal Block Diagram 33926 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS VPWR OUT2 OUT2 OUT2 OUT2 CCP IN2 IN1 SLEW 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 D1 25 24 23 22 NC PGND PGND PGND SF PGND PGND PGND NC Transparent Top View of Package VPWR AGND VPWR INV FB NC AGND 21 20 19 18 10 11 12 13 14 15 16 OUT1 OUT1 OUT1 VPWR OUT1 EN D2 17 Figure 3. 33926 Pin Connections Table 1. 33926 Pin Definitions A functional description of each pin can be found in the Functional Description section beginning on page 12. Pin 1 Pin Name IN2 Pin Function Logic Input Formal Name Input 2 Definition Logic input control of OUT2; e.g., when IN2 is logic HIGH, OUT2 is set to VPWR, and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger input with ~ 80 A source so default condition = OUT2 HIGH.) Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWR, and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with ~ 80 A source so default condition = OUT1 HIGH.) Logic input to select fast or slow slew rate. (Schmitt trigger input with ~ 80 A sink so default condition = slow.) These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. The low current analog signal ground must be connected to PGND via low impedance path (<<10 m, 0 Hz to 20 kHz). Exposed copper pad is also the main heatsinking path for the device. Sets IN1 and IN2 to logic LOW = TRUE. (Schmitt trigger input with ~ 80 A sink so default condition = non-inverted.) Load current feedback output provides ground referenced 0.24% of H-Bridge high-side output current. (Tie pin to GND through a resistor if not used.) No internal connection is made to this pin. When EN is logic HIGH, the device is operational. When EN is logic LOW, the device is placed in Sleep mode. (logic input with ~ 80 A sink so default condition = Sleep mode.) 2 IN1 Logic Input Input 1 3 SLEW Logic Input Slew Rate 4, 6, 11, 31 5, Exposed Pad 7 VPWR AGND Power Input Analog Ground Logic Input Positive Power Supply Analog Signal Ground Input Invert INV 8 9, 17, 25 10 FB NC EN Analog Output Feedback No Connect Logic Input Enable Input 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33926 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description section beginning on page 12. Pin 12, 13, 14, 15 16 Pin Name OUT1 D2 Pin Function Power Output Logic Input Formal Name H-Bridge Output 1 Disable Input 2 (Active Low) Power Ground Definition Source of high-side MOSFET1 and drain of low-side MOSFET1. When D2 is logic LOW, both OUT1 and OUT2 are tri-stated. (Schmitt trigger input with ~80 A sink so default condition = disabled.) High-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the PCB. Open drain active LOW Status Flag output (requires an external pullup resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VCEsat < 0.4 V @ 0.3 mA. Maximum permissible pullup voltage < 7.0 V.) When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger input with ~80 A source so default condition = disabled. Source of high-side MOSFET2 and drain of low-side MOSFET2. External reservoir capacitor connection for internal charge pump; connected to VPWR. Allowable values are 30 F to 100 F. Note This capacitor is required for the proper performance of the device. 18 - 20, 22 - 24 PGND Power Ground 21 SF Logic Output Open Drain Status Flag (Active Low) 26 D1 Logic Input Disable Input 1 (Active High) H-Bridge Output 2 Charge Pump Capacitor 27, 28, 29, 30 32 OUT2 Power Output Analog Output CCP 33926 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. These parameters are not production tested. Ratings ELECTRICAL RATINGS Power Supply Voltage Normal Operation (Steady-State) Transient Overvoltage (1) Logic Input Voltage SF Output (3) (4) (2) Symbol Value Unit V VPWR(SS) VPWR(t) VIN V SF IOUT(CONT) VESD1 - 0.3 to 28 - 0.3 to 40 - 0.3 to 7.0 - 0.3 to 7.0 5.0 V V A V 500 2000 Continuous Output Current ESD Voltage (5) Human Body Model OUT1 and OUT2 to GND All Other Pins Machine Model Charge Device Model Corner Pins (1,9,17,25) All Other Pins THERMAL RATINGS Storage Temperature Operating Temperature Ambient Junction (6) VESD2 200 750 500 TSTG TA TJ - 65 to 150 C C - 40 to 125 - 40 to 150 Notes 1. Device will survive repetitive transient overvoltage conditions for durations not to exceed 500 ms @ duty cycle not to exceed 10%. External protection is required to prevent device damage in case of a reverse battery condition. 2. Exceeding the maximum input voltage on IN1, IN2, EN, INV, SLEW, D1, or D2 may cause a malfunction or permanent damage to the device. 3. Exceeding the pullup resistor voltage on the open drain SF pin may cause permanent damage to the device. 4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature 150C. 5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief non-repetitive excursions of junction temperature above 150C can be tolerated provided the duration does not exceed 30 seconds maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.) 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. These parameters are not production tested. Ratings Peak Package Reflow Temperature During Reflow (7), (8) Approximate Junction-to-Board Thermal Resistance (9) Symbol TPPRT RJB Value 250 < 1.0 Unit C C/W Notes 7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 8. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), 9. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RJB (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum die temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RJA must be < 5.0C/W for maximum current at 70C ambient. Module thermal design must be planned accordingly. 33926 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 8.0 V VPWR 28 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic POWER INPUTS (VPWR) Operating Voltage Range (10) Steady-State Transient (t < 500 ms) (11) Quasi-Functional (RDS(ON) May Increase by 50%) Sleep State Supply Current (12) EN, D2, INV, SLEW = Logic [0], IN1, IN2, D1 = Logic [1], and IOUT = 0 A Standby Supply Current (Part Enabled) IOUT = 0 A, VEN = 5.0 V Undervoltage Lockout Thresholds VPWR(falling) VPWR(rising) Hysteresis CHARGE PUMP Charge Pump Voltage (CP Capacitor = 33 nF) VPWR = 5.0 V VPWR = 28 V CONTROL INPUTS Operating Input Voltage (EN, IN1, IN2, D1, D2, INV, SLEW) Input Voltage (IN1, IN2, D1, D2, INV, SLEW) Logic Threshold HIGH Logic Threshold LOW Hysteresis Input Voltage (EN) Threshold Logic Input Currents, VPWR = 8.0V Inputs EN, D2, INV, SLEW (internal pull-downs), VIH = 5.0V Inputs IN1, IN2, D1 (internal pull-ups), VIL = 0V (13) Symbol Min Typ Max Unit V VPWR(SS) VPWR(t) VPWR(QF) IPWR(SLEEP) - IPWR(STANDBY) - - 20 - 50 mA 8.0 - 5.0 - - - 28 40 8.0 A VUVLO(ACTIVE) VUVLO(INACTIVE) VUVLO(HYS) 4.15 - 150 - - 200 - 5.0 350 V V mV VCP - VPWR 3.5 - - - - 12 V VI VIH VIL VHYS VTH IIN - - 5.5 V 2.0 - 250 1.0 - - 400 - - 1.0 - 2.0 V V mV V A 20 -200 80 -80 200 -20 Notes 10. Device specifications are characterized over the range of 8.0 V VPWR 28 V. Continuous operation above 28 V may degrade device reliability. Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent. 11. Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once every 10 seconds. 12. IPWR(sleep) is with Sleep mode activated and EN, D2, INV, SLEW = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating. 13. SLEW Input Voltage Hysteresis is guaranteed by design. 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR 28 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic POWER OUTPUTS OUT1, OUT2 Output-ON Resistance (15), ILOAD = 3.0A VPWR = 8.0V, TJ = 25C VPWR = 8.0V, TJ = 150C VPWR = 5.0V, TJ = 150C Output Current Regulation Threshold TJ < TFB TJ TFB (Fold back Region - see Figure 9 and Figure 11) (14) High-Side Short Circuit Detection Threshold (Short Circuit to Ground) (14) Low-Side Short Circuit Detection Threshold (Short Circuit to VPWR) Output Leakage Current VOUT = VPWR VOUT = Ground Output MOSFET Body Diode Forward Voltage Drop IOUT = 3.0 A Overtemperature Shutdown (14) Thermal Limit @ TJ Hysteresis @ TJ Current Foldback at TJ(14) Current Foldback to Thermal Shutdown Separation (14) HIGH-SIDE CURRENT SENSE FEEDBACK Feedback Current (pin FB sourcing current) (17) I OUT = 0 mA I OUT = 300 mA I OUT = 500 mA I OUT = 1.5 A I OUT = 3.0 A I OUT = 6.0 A STATUS FLAG (18) Status Flag Leakage Current (19) V SF = 5.0 V Status Flag SET Voltage (20) I SF = 300 A Notes 14. 15. 16. 17. 18. 19. 20. VSFLOW - - 0.4 ISFLEAK - - 5.0 V A I FB 0.0 0.0 0.35 2.86 5.71 11.43 - 270 0.775 3.57 7.14 14.29 50 750 1.56 4.28 8.57 17.15 A A mA mA mA mA TLIM THYS TFB TSEP 175 - 165 10 - 12 - - 200 - 185 15 C C VF - - 2.0 C (16) (14) Symbol Min Typ Max Unit RDS(ON) - - - ILIM 5.2 - ISCH ISCL IOUTLEAK - -60 - - 100 - 11 9.0 6.5 4.2 13 11 8.0 - 16 14 120 - - - 225 325 m A A A A , Outputs off, VPWR = 28V V This parameter is Guaranteed By Design. Output-ON resistance as measured from output to VPWR and from output to GND. Outputs switched OFF via D1 or D2. Accuracy is better than 20% from 0.5 A to 6.0 A. Recommended terminating resistor value: RFB = 270 . Status Flag output is an open drain output requiring a pullup resistor to logic VDD. Status Flag Leakage Current is measured with Status Flag HIGH and not SET. Status Flag Set Voltage measured with Status Flag LOW and SET with I FS = 300 A. Maximum allowable sink current from this pin is < | 500 A | . Maximum allowable pullup voltage < 7.0 V. 33926 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 8.0 V VPWR 28 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic TIMING CHARACTERISTICS PWM Frequency (21) Maximum Switching Frequency During Current Limit Regulation (22) Output ON Delay (23) VPWR = 14 V Output OFF Delay (23) VPWR = 14 V ILIM Output Constant-OFF Time (24) ILIM Blanking Time (25) Disable Delay Time (26) Output Rise and Fall Time SLEW = SLOW SLEW = FAST Short Circuit / Overtemperature Turn-OFF (Latch-OFF) Time (28) (29) Power-ON Delay Time (29) Output MOSFET Body Diode Reverse Recovery Time (29) Charge Pump Operating Frequency (29) t FAULT t POD tRR fCP (27) Symbol Min Typ Max Unit f PWM f MAX t DON - - - - 20 20 kHz kHz s - t DOFF - tA tB t DDISABLE t F, t R 1.5 0.2 - - 75 - 15 12 - - 18 s - 20.5 16.5 - 12 32 27 8.0 s s s s 3.0 - - 1.0 100 7.0 6.0 1.45 8.0 5.0 150 - s ms ns MHz Notes 21. The maximum PWM frequency is obtained when the device is set to Fast Slew Rate via the SLEW pin. PWM-ing when SLEW is set to SLOW should be limited to frequencies < 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side MOSFETs. 22. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load's inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM frequency during current limit. 23. Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5V on the input signal to the 80% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5V on the input signal to the 20% point of the output response signal. See Figure 4, page 10. 24. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge. 25. The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time to act. 26. Disable Delay Time measurement is defined in Figure 5, page 10. 27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR = 14 V, RLOAD = 3.0 ohm. See Figure 6, page 10. 28. Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short circuit currents possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode may cause junction temperatures to rise. Junction temperatures above ~160C will cause the output current limit threshold to "fold back", or decrease, until ~175C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this fold back region is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9). Parameter is Guaranteed By Design. 29. 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS VIN1, IN2 (V) 5.0 1.5V 0 VPWR t DON 80% 20% 0 TIME t DOFF 1.5V VOUT1, 2 (V) Figure 4. Output Delay Time VD1, D2 (V) 5.0 V 1.5V 0V IO = 100mA tDDISABLE VOUT1, 2 90% 0 TIME Figure 5. Disable Delay Time . VOUT1, 2 (V) VPWR tF tR 90% 0 90% 10% TIME 10% Figure 6. Output Switching Time Overload Condition 9.0 IOUT, CURRENT (A) ISC Short Circuit Detection Threshold tB 6.5 Ilim tA tB = Ilim Blanking Time tA = Constant-OFF Time (OUT1 and OUT2 Tri-Stated) 0.0 5.0 t ON TIME Figure 7. Current Limit Blanking Time and Constant-OFF Time 33926 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS Short Circuit Condition t FAULT ISC Short Circuit Detection Threshold Hard Short Occurs tB 6.5 Ilim OUT1, OUT2 Tri-Stated, SF set Low 9.0 IOUT, CURRENT (A) 0.0 5.0 t B (~16 us) TIME Figure 8. Short Circuit Detection Turn-OFF Time tFAULT . Nominal Current Limit Threshold Current Limit Threshold Foldback. Operation within this region must be limited to non-repetitive events not to exceed 30 s per 24 hr. ILIM CURRENT (A) 6.5 4.2 TSEP THYS TFB TLIM TLIM Thermal Shutdown Figure 9. Output Current Limiting Foldback Region 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop control) make the 33926 a very attractive, costeffective solution for controlling a broad range of small DC motors. The 33926 outputs are capable of supporting peak DC load currents of up to 5.0 A from a 28 VPWR source. An internal charge pump and gate drive circuitry are provided that can support external PWM frequencies up to 20 kHz. The 33926 has an analog feedback (current mirror) output pin (the FB pin) that provides a constant-current source ratioed to the active high-side MOSFETs' current. This can be used to provide "real time" monitoring of output current to facilitate closed-loop operation for motor speed/torque control, or for the detection of open load conditions. Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. An input invert, INV, changes IN1 and IN2 to LOW = true logic. Two different output slew rates are selectable via the SLEW input. Two independent disable inputs, D1 and D2, provide the means to force the H-Bridge outputs to a high impedance state (all HBridge switches OFF). An EN pin controls an enable function that allows the IC to be placed in a power-conserving Sleep mode. The 33926 has Output Current Limiting (via Constant OFF-Time PWM Current Regulation), Output Short-Circuit Detection with Latch-OFF, and Overtemperature Detection with Latch-OFF. Once the device is latched-OFF due to a fault condition, either of the Disable inputs (D1 or D2), VPWR, or EN must be "toggled" to clear the status flag. Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold triggering. The current limiting scheme is unique in that it incorporates a junction temperaturedependent current limit threshold. This means that the current limit threshold is "reduced to around 4.2 A" as the junction temperature increases above 160C. When the temperature is above 175C, overtemperature shutdown (latch-OFF) will occur. This combination of features allows the device to continue operating for short periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. FUNCTIONAL PIN DESCRIPTION POWER GROUND AND ANALOG GROUND (PGND AND AGND) The power and analog ground pins should be connected together with a very low impedance connection. that the current is being commanded to flow through the load attached between OUT1 and OUT2, changing the logic level at INV will have the effect of reversing the direction of current commanded. Thus, the INV input may be used as a "forward/ reverse" command input. If both IN1 and IN2 are the same logic level, then changing the logic level at INV will have the effect of changing the bridge's output from freewheeling high to freewheeling low or vice versa. POSITIVE POWER SUPPLY (VPWR) VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as short as possible traces, offering as low impedance as possible between pins. Transients on VPWR which go below the Under Voltage Threshold will result in the protection activating. It is essential to use an input filter capacitor of sufficient size and low ESR to sustain a VPWR greater than VUVLO when the load is switched (See 33926 Typical Application Schematic on page 18). SLEW RATE (SLEW) The SLEW pin is the logic input that selects fast or slow slew rate. Schmitt trigger input with ~ 80 A sink so the default condition is SLOW. When SLEW is set to SLOW, PWM-ing should be limited to frequencies less than 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side MOSFETs. STATUS FLAG (SF) This pin is the device fault status output. This output is an active LOW open drain structure requiring a pullup resistor to VDD. The maximum VDD is < 7.0 V. Refer to Table 5, Truth Table, page 16 for the SF Output status definition. INPUT 1,2 AND DISABLE INPUT 1,2 (IN1, IN2, AND D1, D2) These pins are input control pins used to control the outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible inputs with hysteresis. IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complementary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the INPUT INVERT (INV) The Input Invert Control pin sets IN1 and IN2 to LOW = TRUE. This is a Schmitt trigger input with ~ 80 A sink; the default condition is non-inverted. If IN1 and IN2 are set so 33926 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION device circuitry is fully operational and the supply IPWR(STANDBY) current is reduced to a few mA. Refer to Table 3, Static Electrical Characteristics, page 7. H-BRIDGE OUTPUT (OUT1, OUT2) These pins are the outputs of the H-Bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The outputs have PWM current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) is incorporated to distinguish between load currents that are higher than the ILIM threshold and short circuit currents. This timer is activated at each output transition. a logic LOW state, the device is in the Sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pulldown resistor maintains the device in Sleep mode in the event EN is driven through a high impedance I/O or an unpowered microcontroller, or the EN input becomes disconnected. FEEDBACK (FB) The 33926 has a feedback output (FB) for "real time" monitoring of H-Bridge high-side output currents to facilitate closed-loop operation for motor speed and torque control. The FB pin provides current sensing feedback of the H-Bridge high-side drivers. When running in the forward or reverse direction, a ground-referenced 0.24% of load current is output to this pin. Through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can "read" the current proportional voltage with its analog-to-digital converter (ADC). This is intended to provide the user with only first-order motor current feedback for motor torque control. The resistance range for the linear operation of the FB pin is 100 < RFB < 300 W. If PWM-ing is implemented using the disable pin inputs (either D1 or D2), a small filter capacitor (~1.0 F) may be required in parallel with the RFB resistor to ground for spike suppression. CHARGE PUMP CAPACITOR (CCP) This pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. The allowable value is from 30 nF to 100 nF. This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot operate properly without the external reservoir capacitor. ENABLE INPUT (EN) The EN pin is used to place the device in a Sleep mode so as to consume very low currents. When the EN pin voltage is 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION 33926 CURRENT SENSE VOLTAGE REGULATION TEMPERATURE SENSE CHARGE PUMP H-BRIDGE OUTPUT DRIVERS ANALOG CONTROL AND PROTECTION PWM CONTROLLER OUT1 - OUT2 MCU INTERFACE COMMAND AND FAULT REGISTERS PROTECTION LOGIC CONTROL GATE CONTROL LOGIC Figure 10. Functional Internal Block Diagram ANALOG CONTROL AND PROTECTION CIRCUITRY: The on-chip Voltage Regulator supplies 3.3V to the internal logic. The charge pump provides gate drive for the HBridge MOSFETs. The Current and Temperature sense circuitry provides detection and protection for the output drivers. Output undervoltage protection shuts down the MOSFETS. two half-bridge totem-pole outputs. Two independent disable inputs are provided to force the H-Bridge outputs to tri-state (high impedance off-state). H-BRIDGE OUTPUT DRIVERS: OUT1 AND OUT2 The H-Bridge is the power output stage. The current flow from OUT1 to OUT2 is reversible and under full control of the user by way of the Input Control Logic. The output stage is designed to produce full load control under all system conditions. All protective and control features are integrated into the Control and Protection blocks. The sensors for current and temperature are integrated directly into the output MOSFET for maximum accuracy and dependability. GATE CONTROL LOGIC: The 33926 is a monolithic H-Bridge Power IC designed primarily for any low-voltage DC servo motor control application within the current and voltage limits stated for the device. Two independent inputs provide polarity control of 33926 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES ILOAD, OUTPUT CURRENT (A) 9.0 6.5 PWM Current Limiting Typical Short Circuit Detection Threshold Typical Current Limit Threshold High Current Load Being Regulated via Constant-OFF-Time PWM Moderate Current Load Hard Short Detection and Latch-OFF 0 IN1 or IN2 IN1 or IN2 INn, LOGIC IN [1] IN1 IN2 [0] IN2 or IN1 IN2 or IN1 D1, LOGIC IN D2, LOGIC IN SF, LOGIC OUT [1] [0] [1] [0] [1] Outputs [0] Tri-Stated Outputs Operation (per Input Control Condition) Time Outputs Tri-Stated Figure 11. Operating States 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS Table 5. Truth Table The tri-state conditions and the status flag are reset using D1 or D2. The truth table uses the following notations: L = LOW, H = HIGH, X = HIGH or LOW, and Z = High Impedance. All output power transistors are switched off. Device State Forward Reverse Free Wheeling Low Free Wheeling High Disable 1 (D1) Disable 2 (D2) IN1 Disconnected IN2 Disconnected D1 Disconnected D2 Disconnected Input Conditions EN H H H H H H H H H H L L L L H X L L Z X X X X X X D1 H H H H X L H H X Z X X X X X D2 H L L H X X Z X X X X X X X X IN1 L H L H X X X Z X X X X X X X IN2 Status SF H H H H L L H H L L L L L H H H L L H Z Z H X Z Z Z Z Z Z Z Outputs OUT1 L H L H Z Z X H Z Z Z Z Z Z Z OUT2 Undervoltage Lockout Overtemperature Short Circuit (31) (31) (30) H H H L Z Sleep Mode EN EN Disconnected Notes 30. In the event of an undervoltage condition, the outputs tri-state and status flag is SET logic LOW. Upon undervoltage recovery, status flag is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 31. When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals and the status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1, D2, EN, or VPWR. Forward V PW R Load Current ON OUT1 LOAD OFF OUT2 V PW R High-Side Recirculation (Forward) VPWR VPWR Reverse V PW R Load Current V PW R Low-Side Recirculation (Forward) VPWR VPWR ON OUT1 Load Current OFF ON LOAD OUT2 ON OUT1 OFF OUT1 LOAD Load Current OFF OUT2 LOAD OUT2 ON OFF ON OFF OFF PGND PGND OFF PGND ON ON PGND PGND PGND PGND PGND Figure 12. 33926 Power Stage Operation 33926 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES PROTECTION AND DIAGNOSTIC FEATURES SHORT CIRCUIT PROTECTION If an output short circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and the fault status output flag (SF) is SET to logic LOW. If the D1 input changes from logic HIGH to logic LOW, or if the D2 input changes from logic LOW to logic HIGH, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic HIGH state. The output stage will always switch into the mode defined by the input pins (IN1, IN2, D1, and D2), provided the device junction temperature is within the specified operating temperature range. OVERTEMPERATURE SHUTDOWN AND HYSTERESIS If an overtemperature condition occurs, the power outputs are tri-stated (latched-OFF) and the fault status flag (SF) is SET to logic LOW. To reset from this condition, D1 must change from logic HIGH to logic LOW, or D2 must change from logic LOW to logic HIGH. When reset, the output stage switches ON again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. Important Resetting from the fault condition will clear the fault status flag. Powering down and powering up the device will also reset the 33926 from the fault condition. INTERNAL PWM CURRENT LIMITING The maximum current flow under normal operating conditions should be less than 5.0 A. The instantaneous load currents will be limited to ILIM via the internal PWM current limiting circuitry. When the ILIM threshold current value is reached, the output stages are tri-stated for a fixed time (T A) of 20 s typical. Depending on the time constant associated with the load characteristics, the output current decreases during the tri-state duration until the next output ON cycle occurs. The PWM current limit threshold value is dependent on the device junction temperature. When - 40C < TJ < 160C, ILIM is between the specified minimum/maximum values. When TJ exceeds 160 C, the ILIM threshold decreases to 4.2 A. Shortly above 175 C the device overtemperature circuit will detect TLIM and an overtemperature shutdown will occur. This feature implements a graceful degradation of operation before thermal shutdown occurs, thus allowing for intermittent unexpected mechanical loads on the motor's gear-reduction train to be handled. Important Die temperature excursions above 150C are permitted only for non-repetitive durations < 30 seconds. Provision must be made at the system level to prevent prolonged operation in the current-foldback region. OUTPUT AVALANCHE PROTECTION If VPWR were to become an open circuit, the outputs would likely tri-state simultaneously due to the disable logic. This could result in an unclamped inductive discharge. The VPWR input to the 33926 should not exceed 40 V during this transient condition, to prevent electrical overstress of the output drivers.This can be accomplished with a zener clamp or MOV, and/or an appropriately valued input capacitor with sufficiently low ESR (see Figure 13). VPW R VPW R Bulk Low ESR Cap. 100nF OUT1 M 9 I/Os OUT2 AGND PGND Figure 13. Avalanche Protection 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 17 TYPICAL APPLICATIONS INTRODUCTION TYPICAL APPLICATIONS INTRODUCTION A typical application schematic is shown in Figure 14. For precision high-current applications in harsh, noisy environments, the VPWR by-pass capacitor may need to be substantially larger. VPWR 100F LOW ESR 100nF VPWR 33NF VDD LOGIC SUPPLY CCP EN IN1 IN2 D2 D1 +5.0V STATUS FLAG TO ADC RFB 270 INV SLEW SF FB VCP CHARGE PUMP TO GATES HS1 LS1 HS2 GATE DRIVE AND PROTECTION LOGIC LS2 VSENSE ILIM PWM HS1 HS2 OUT1 M OUT2 LS1 LS2 PGND CURRENT MIRRORS AND CONSTANT OFF-TIME PWM CURRENT REGULATOR 1.0F AGND PGND Figure 14. 33926 Typical Application Schematic 33926 18 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed below. PNB SUFFIX 98ARL10579D 32-PIN PQFN ISSUE C 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 19 PACKAGING PACKAGE DIMENSIONS PNB SUFFIX 98ARL10579D 32-PIN PQFN ISSUE C 33926 20 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) Introduction This thermal addendum is provided as a supplement to the MC33926 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations The MC33926 is offered in a 32 pin PQFN, single die package. There is a single heat source (P), a single junction temperature (TJ), and thermal resistance (RJA). TJ = 33926 32-PIN PQFN RJA . P The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. PNB SUFFIX 98ARL10579D 32-PIN PQFN 8.0 mm x 8.0 mm Note For package dimensions, refer to the 33926 data sheet. STANDARDS Table 6. Thermal Performance Comparison Thermal Resistance JA JB (1),(2) (2),(3) [C/W] 28 12 80 1.0 0.2 1.0 1.0 JA (1), (4) (5) 0.2 * All measurements are in millimeters Notes 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated. Figure 15. Surface Mount for Power PQFN with Exposed Pads 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 21 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) VPWR OUT2 OUT2 OUT2 OUT2 CCP IN2 IN1 SLEW VPWR AGND VPWR INV FB NC 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 D1 25 24 23 22 NC PGND PGND PGND SF PGND PGND PGND NC A AGND 21 20 19 18 10 11 12 13 14 15 16 VPWR OUT1 OUT1 OUT1 OUT1 EN D2 17 33926PNB Pin Connections 32-Pin PQFN 0.80 mm Pitch 8.0 mm x 8.0 mm Body Figure 16. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 7. Thermal Resistance Performance A [mm2] 0 300 600 JA [C/W] 81 49 40 Outline: Area A: Ambient Conditions: JA . 33926 22 Analog Integrated Circuit Device Data Freescale Semiconductor ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) 90 80 Thermal Resistance [C/W] 70 60 50 40 30 20 10 0 x JA [C/W] 0 300 Heat Spreading Area A [mm] 600 Figure 17. Device on Thermal Test Board JA 100 Thermal Resistance [C/W] 10 1 x JA [C/W] 0.1 1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s] Figure 18. Transient Thermal Resistance RJA, 1 W Step response, Device on Thermal Test Board Area A = 600 (mm2) 33926 Analog Integrated Circuit Device Data Freescale Semiconductor 23 REVISION HISTORY REVISION HISTORY REVISION DATE 1.0 2.0 3.0 4.0 5.0 6.0 3/2006 6/2007 10/2006 12/2006 2/2007 3/2007 DESCRIPTION * Updated formatting and technical content throughout entire document. * Updated formatting and technical content throughout entire document * Updated formatting and technical content throughout entire document * Updated formatting and technical content throughout entire document * Updated formatting and technical content throughout entire document * Changed Human Body Model, Charge Pump Voltage (CP Capacitor = 33 nF), No PWM and PWM = 20kHz, Slew Rate = Fast, Output Rise and Fall Time (27) * Added second paragraph to Positive Power Supply (VPWR) * Added "Low ESR" to 100F on 33926 Typical Application Schematic * Changed status to Advance Information 7.0 6/2007 33926 24 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2007. All rights reserved. MC33926 Rev. 7.0 6/2007 |
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